Hardware vs. software Transactional memory

hardware transactional memory using read , write bits

the abstraction of atomicity in transactional memory requires hardware mechanism detect conflicts , undo changes made shared data. hardware transactional memory systems may comprise modifications in processors, cache , bus protocol support transactions. speculative values in transaction must buffered , remain unseen other threads until commit time. large buffers used store speculative values while avoiding write propagation through underlying cache coherence protocol. traditionally, buffers have been implemented using different structures within memory hierarchy such store queues or caches. buffers further away processor, such l2 cache, can hold more speculative values (up few megabytes). optimal size of buffer still under debate due limited use of transactions in commercial programs. in cache implementation, cache lines augmented read , write bits. when hardware controller receives request, controller uses these bits detect conflict. if serializability conflict detected parallel transaction, speculative values discarded. when caches used, system may introduce risk of false conflicts due use of cache line granularity. load-link/store-conditional (ll/sc) offered many risc processors can viewed basic transactional memory support; however, ll/sc operates on data size of native machine word, single-word transactions supported. although hardware transactional memory provides maximal performance compared software alternatives, limited use has been seen @ time.

software transactional memory provides transactional memory semantics in software runtime library or programming language, , requires minimal hardware support (typically atomic compare , swap operation, or equivalent). downside, software implementations come performance penalty, when compared hardware solutions. hardware acceleration can reduce of overheads associated software transactional memory.

owing more limited nature of hardware transactional memory (in current implementations), software using may require extensive tuning benefit it. example, dynamic memory allocator may have significant influence on performance , likewise structure padding may affect performance (owing cache alignment , false sharing issues); in context of virtual machine, various background threads may cause unexpected transaction aborts.